The Intel x86 architecture has modes: 1. real vs. protected modes on for 32 bit 2. long vs. flat modes on 64 bit ### Segmentation - Address space is divided in variable sized logical units called segments - Segments are divided further into pages. Pages are of fixed sizes (4KB and big pages) ![[attachments/Screenshot 2023-05-23 at 9.58.05 PM.png]] `Logical address = (segment number, page number, page offset)` ## Address translation Segment table translates between logical and physical addresses. `logical address = (segment number, displacement)` $physical address = *(SGTBR+ STE * STE Size) + displacement$ where, $SGTBR$ = Segment Table Base Register, this is where the segment table starts. $STE$ = Segment Table Entry Number Intuition: We start at the segment table base register (`SGTBR`), the starting location of the register. $STE*STE\space size$ calculates the location of the segment relative to the register. $*(SGTBR+STE*STE Size)$ is C pointer notation for finding the location in physical memory. We add the displacement to find the physical address. In case we have paging, `STE` can point to page table base of the segment page table. Some checks are performed to ensure we access physical memory belonging to the process, $displacement \le segment size$. Segment tables are also called descriptor tables, and there are separate tables - for user mode (Local Descriptor Table or LDT), and - system mode execution (Global Descriptor Table or GDT). ### 32-bit translation ![[attachments/Screenshot 2023-05-23 at 10.13.13 PM.png|Segmentation & paging in Intel x86]] In 32-bit architectures, we take the logical address (or far pointer) and calculate the linear address, which allows us to calculate the physical address. (Diagram above) > [!example] logical address (segment selector + offset) → linear address (page table entry + offset) → physical address (actual address) ## x86 address translation ![[attachments/Screenshot 2023-05-23 at 10.38.48 PM.png|Linear-addrtess translation to 4-KB page using IA-32e paging]] 64 bit architectures has no GDT that maps to a linear address, we iteratively apply an offset to a memory location that brings us to the next memory location. Ultimately we end up in the physical memory as in 32 bit architectures. PML4 stands for "Page map level 4" and CR3 is a register that points to its location. > [!Example] Register CR3 → Page Map Level 4 (PML4E) → Page-Directory Pointer Table (PDPTE) → Page-Directory → Page Table → Physical Address ### Some observations > [!faq]- Where in the address space do the page/segment tables get allocated? > In the TCB/OS part of the address space The tables used in address translation determine what physical memory we can access. Therefore they must belong to the OS's memory so that the user cannot modify them. If the user can modify the tables there is no isolation. We ensure isolation between different programs as well as user and system level. > [!faq]- Who can load these registers? > Special (privileged) instructions that can only be mediated by the TCB Translating logical to physical addresses could really slow down the program, but the hardware has a *Translation Lookaside Buffer (TLB)* which stores mappings from logical addresses to physical addresses. ---- #comfort-hard